1. Field of Invention
The present invention relates to a configurable flip flop circuit, and in particular, to a configurable flip flop circuit for use in a field programmable gate array (FPGA).
2. Description of Related Art
FIG. 1 is a schematic diagram of a prior art flip flop circuit 100 used in a programmable device such as an FPGA. Flip flop circuit 100 includes D flip flop 101, and two-tone multiplexers 102 and 103. Flip flop circuit 100 is coupled to programmable logic block 105 as described below. The Q output terminal of flip flop 101 is connected to the "0" input terminal of multiplexer 103. The Q output terminal of flip flop 101 is also connected to an input terminal of programmable logic block 105 through programmable interconnect circuitry (not shown). Using a digital counter circuit as an example, programmable logic block 105 implements an adder circuit 104 which increments the signal at the Q output terminal of flip flop 101 by one. The output terminal of adder circuit 104 is connected to the "1" input terminal of multiplexer 103. The signal at the output terminal of multiplexer 103 is either equal to the contents of flip flop 101 or the contents of flip flop 101 incremented by one, depending upon the status of the count enable signal provided to the control terminal of multiplexer 103. When the count enable signal is in a logic low state (i.e., "0"), the signal at the "0" input terminal of multiplexer 103 is transmitted through multiplexer 103. Conversely, a logic high count enable signal causes the signal at the "1" input terminal of multiplexer 103 to be transmitted through multiplexer 103. This convention is maintained for the multiplexers described below.
The output terminal of multiplexer 103 is connected to the "0" input terminal of multiplexer 102. The "1" input terminal of multiplexer 102 is connected to a line which receives a data signal. The signal at the output terminal of multiplexer 102 is either equal to the output signal from multiplexer 103 or the data signal, depending upon the status of the load enable signal provided to the control terminal of multiplexer 102. The output terminal of multiplexer 102 is connected to the D input terminal of flip flop 101. Table 1 describes the operation of flip flop circuit 100.
TABLE 1 ______________________________________ Count Enable Load Enable Effect on Contents of Flip Flop 101 ______________________________________ 0 0 Unchanged (No Operation) 0 1 Load Data Signal 1 0 Increment by One 1 1 Load Data Signal ______________________________________
Thus, in flip flop circuit 100, the operation of loading the data signal takes precedence over the operations of incrementing by one and performing no operation. That is, regardless of the status of the count enable signal, a load operation will be performed when the load enable signal is asserted. This method of operating is desired in certain digital counter circuits.
FIG. 2 is a schematic diagram of another prior art flip flop circuit 200. Flip flop circuit 200 includes D flip flop 201, and two-to-one multiplexers 202 and 203. Programmable logic block 205 is coupled to flip flop circuit as described below. The Q output terminal of flip flop 201 is connected to an input terminal of programmable logic block 205 using programmable interconnect circuitry (not shown). Programmable logic block 205 implements an adder circuit 204 which increments the signal at the Q output terminal of flip flop 201 by one. The output terminal of adder 204 is connected to the "0" input terminal of multiplexer 203. The "1" input terminal of multiplexer 203 is connected to a line which receives a data signal. Multiplexer 203 is controlled by a load enable signal.
The output terminal of multiplexer 203 is connected to the "1" input terminal of multiplexer 202. The "0" input terminal of multiplexer 202 is connected to the Q output terminal of flip flop 201. Multiplexer 202 is controlled by a count enable signal. The output terminal of multiplexer 202 is connected to the D input terminal of flip flop 201. Table 2 describes the operation of flip flop circuit 200.
TABLE 2 ______________________________________ Count Enable Load Enable Effect on Contents of Flip Flop 201 ______________________________________ 0 0 Unchanged (No Operation) 0 1 Unchanged (No Operation) 1 0 Increment by One 1 1 Load Data Signal ______________________________________
Thus, in flip flop circuit 200, the "no operation" instruction takes precedence over the operation of loading the data signal and the operation of incrementing the contents of flip flop 201 by one. That is, if the count enable signal is de-asserted low, the "no operation" instruction is implemented, regardless of the state of the load enable signal. This method of operating is desirable in certain digital counter circuits.
Prior art FPGAs are designed to utilize flip flop circuitry in accordance with either flip flop circuit 100 or flip flop circuit 200. The selected flip flop circuit is "hard-wired" during the fabrication of the FPGA. Once the flip flop circuitry is selected and fabricated, this circuitry cannot be easily modified to provide the nonselected flip flop circuitry. Therefore, if flip flop circuit 100 is fabricated on an FPGA, this flip flop circuit cannot later be modified to provide flip flop circuit 200. Because the circuit designer who programs the FPGA may require the use of flip flop circuit 100 and/or flip flop circuit 200, it would be desirable to have a flip flop circuit capable of being configured like flip flop circuit 100 or flip flop circuit 200 at the discretion of the designer, rather than during fabrication.